Conventional semiconductor flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) devices include arrays of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, a group of the cells are erased together as a block.
Flash memory devices of this type may include individual memory cells characterized by a vertical stack of a tunnel oxide (e.g., SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate, and a control gate over the interlayer dielectric. The vertical stack may be formed on a crystalline silicon substrate. The substrate may include a channel region positioned below the vertical stack and source and drain on opposing sides of the channel region. Various voltages may be applied to the cell elements to program the cell with a binary 1 or 0, to erase all or some of the cells as a block, to read the cell, to verify that the cell is erased, or to verify that the cell is not over-erased.
Another type of memory cell structure is characterized by a vertical stack that includes an insulating tunnel oxide layer, a charge trapping nitride layer, an insulating top oxide layer, and a polysilicon control gate, all positioned on top of a crystalline silicon substrate. This particular structure of a silicon channel region, tunnel oxide, nitride, top oxide, and polysilicon control gate is often referred to as a SONOS (silicon-oxide-nitride-oxide-silicon) device.
It is known that as capacitive coupling between the charge storage layer and the control gate of a conventional stacked-gate memory cell is increased, the time taken to programming the cell is decreased. In general, capacitive coupling may be increased by increasing the capacitance, through an increase in the areas of the floating and control gate electrodes. However, because of the continued downscaling of semiconductor memory devices in general, the cell area, and hence the areas of the gate electrodes are necessarily being reduced. As a result, it has been difficult to maintain the suitable coupling levels.
Memory cells in a flash memory device are typically connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective word line and the drains of the cells in a column being connected to a respective bit line. To operate efficiently and reliably, each cell is effectively isolated from neighboring cells.
Unfortunately, conventional shallow trench isolation (STI) fabrication techniques fail to provide stacked cell structures that provide sufficient gate coupling while simultaneously reducing or eliminating deleterious cross-coupling noise between neighboring charge storage elements.